This invention relates to the field of solid state electronics and particularly to a heterostructure complementary transistor switch which is useful in a memory cell.
Complementary transistor switches (CTSs) have been used for memory cells in silicon bipolar random access memory (RAM) circuits. Such a prior art RAM circuit is shown in FIG. 1 (IBM Journal Research Development, Vol. 25, No. 3, May 19871, pp. 126-134). These complementary transistor switches have good stability and use little standby power.
Although silicon has proven to be a very useful and practical semiconductor, the performance of integrated circuits such as complementary transistor switch memory cells is ultimately limited by the properties of the semiconductor used. For this reason, new integrated circuit devices are being developed to take advantage of the properties of Group III-V semiconducting compounds such as GaAs. For example, GaAs heterojunction bipolar transistors (HBTs) with lower internal resistance than Si HBTs can be obtained using high base doping concentration in the GaAs.
Additionally, integrated circuits in prior art silicon devices use a horizontal layout in which individual devices are formed on the surface of the chip, requiring spacing between the electrodes. Consequently, the number of CTSs that can be packed onto a given area is lower than could be obtained using a vertical structure with an aspect ratio near unity. In addition to conserving chip area, a higher packing density also provides higher operating speed.